1. Field of the Invention
The present invention relates to an automatic hold time fixing circuit unit and, more particularly, to an automatic hold time fixing circuit unit capable of automatically increasing the sufficient delay time to avoid erroneous data output resulting from an unbalanced clock tree.
2. Description of the Related Art
Hold time fixing is required in a sequential circuit especially when the clock tree is unbalanced. FIG. 1 shows a conventional sequential circuit including two flip-flops FFA and FFB and two combinational logic circuit units CC1 and CC2. The flip-flop FFA includes a data output port u, and the flip-flop FFB includes a data input port v. The combinational logic circuit units CC1 and CC2 are well-known circuits in the art and can perform various circuit operational functions. Each combinational logic circuit unit CC1, CC2 has data input port i allowing input of data.
With reference to FIG. 1, when the flip-flop FFA is triggered by a clock a, data inputted via a data input port I is transferred by the flip-flop FFA to the combinational logic circuit unit CC1 for processing purposes and then to the combinational logic circuit unit CC2 for other processing purposes. Then, the data is sent to the data input port v of the flip-flop FFB, so that the data can be sent out to a data output port O when the flip-flop FFB is triggered by another clock b.
FIG. 2a is a timing diagram of the sequential circuit of FIG. 1 in an ideal state, showing the ideal data value of the data input port v between the n−1th trigger and n+2th trigger of the clocks a and b. When the clock b proceeds with the n−1th trigger, the flip-flop FFB acquires the N−1th data value at the data input port v. When the clock b proceeds with the nth trigger, the flip-flop FFB acquires the Nth data value at the data input port v. Likewise, the flip-flop FFB acquires the N+1th and N+2th data values at the data input port v when the clock b proceeds with the n+1th and n+2th triggers.
FIG. 2b is a timing diagram of the sequential circuit resulting from an unbalanced clock tree. Specifically, the flip-flop FFB acquires erroneous data values between the n−1th trigger and n+2th trigger of the clocks a and b due to an unbalanced clock tree between the clocks a and b.
With reference to FIG. 2b and also to FIG. 2a, the clock b has a lag z behind the clock a; namely, the clock tree is unbalanced. When the clock b proceeds with the n−1th trigger, the flip-flop FFB will erroneously acquire the Nth data values at the data input port v. When the clock b proceeds with the nth trigger, the flip-flop FFB will erroneously acquire the N+1th data value at the data input port v. Likewise, the flip-flop FFB will acquire the N+2th and N+3th data values at the data input port v when the clock b proceeds with the n+1th and n+2th triggers.
In an attempt to solve the above problems, the delay time between the data output port u and the data input port v has to be increased, so that the flip-flop FFB can acquire the correct data value at the data input port v when the clock b proceeds with trigger. Namely, when unbalanced clock tree occurs in sequential circuits, the delay time need to be additionally increased to fix the problems.
Conventionally, a passive delay circuit is added based on the required hold time in a combinational hold time circuit approach for solving the hold time problem in sequential circuits. FIG. 3 shows a conventional sequential circuit with hold time fixing function by adding a combinational hold time circuit unit D1 between the combinational logic circuit units CC1 and CC2. The combinational hold time circuit unit D1 is a well-known circuit in the art for estimating the lag z by timing analysis. At least one delay cell is added into the sequential circuit of FIG. 1 based on the operational result of the operational circuit, so that the data inputted to the sequential circuit during the lag z is held and not outputted via the data output port O until the clocks a and b are both at “on” level.
However, the more need in hold time, the more delay cells are required in the circuits. As a result, the area occupied by the combinational hold time circuit becomes larger. The manufacturing costs of the hold time circuit are increased. Furthermore, the connection arrangement between the delay cells and the sequential circuit is more difficult.
Thus, a need exists for an improved hold time fixing circuit unit for solving the above problems.